(from "linux/arch/i386/kernel/head.S")
The boot code in "linux/arch/i386/boot/setup.S" transfers execution to the beginning code in "linux/arch/i386/kernel/head.S" (labeled "startup_32:").
To get to this point, a small uncompressed kernel function decompresses the remaining compressed kernel image and then it jumps to the new kernel code.
This is a description of what the "head.S" code does.
swapper_pg_dir is the top-level page directory, address 0x00101000.
On entry, %esi points to the real-mode code as a 32-bit pointer.
Set the %ds, %es, %fs, and %gs registers to __KERNEL_DS.
#ifdef CONFIG_SMP
If %bx is zero, this is a boot on the Bootstrap Processor (BSP), so skip this. Otherwise, for an AP (Application Processor):
If the desired %cr4 setting is non-zero, turn on the paging options (PSE, PAE, ...) and skip "Initialize page tables" (jump to "Enable paging").
#endif /* CONFIG_SMP */
Begin at pg0 (page 0) and init all pages to 007 (PRESENT + RW + USER). .:: telegra.ph ::.
Set %cr3 (page table pointer) to swapper_pg_dir.
Set the paging ("PG") bit of %cr0 to
********** enable paging **********.
Jump $ to flush the prefetch queue.
Jump *[$] to make sure that %eip is relocated.
Setup the stack pointer (lss stack_start, %esp).
#ifdef CONFIG_SMP
If this is not the BSP (Bootstrap Processor), clear all flags bits and jump to checkCPUtype.
#endif /* CONFIG_SMP */
The BSP clears all of BSS (area between __bss_start and _end) for the kernel.
Setup the IDT for 32-bit mode (call setup_idt). setup_idt sets up an IDT with 256 entries pointing to the default interrupt handler "ignore_int" as interrupt gates. It doesn't actually load the IDT; that can be done only after paging has been enabled and the kernel moved to PAGE_OFFSET. Interrupts are enabled elsewhere, when we can be relatively sure everything is OK. .:: computer.ju.edu.jo ::.
Clear the eflags register (before switching to protected mode).
First 2 KB of _empty_zero_page is for boot parameters, second 2 KB is for the command line.
Initialize X86_CPUID to -1.
Use Flags register, push/pop results, and CPUID instruction(s) to determine CPU type and vendor: Sets X86, X86_CPUID, X86_MODEL, X86_MASK, and X86_CAPABILITY. Sets bits in %cr0 accordingly. .:: cosloodwmn571.wixsite.com ::.
Also checks for presence of an 80287 or 80387 coprocessor. Sets X86_HARD_MATH if a math coprocessor or floating point unit is found.
For CONFIG_SMP builds, increment the "ready" counter to keep a tally of the number of CPUs that have been initialized.
Load GDT with gdt_descr and IDT with idt_descr. The GDT contains 2 entries for the kernel (4 GB each for code and data, beginning at 0) and 2 userspace entries (4 GB each for code and data, beginning at 0). There are 2 null descriptors between the userspace descriptors and the APM descriptors. [Code: Spring Framework]
The GDT also contains 4 entries for APM segments. The APM segments have byte granularity and their bases and limits are set at runtime.
The rest of the gdt_table (after the APM segments) is space for TSSes and LDTs. .:: www.slideshare.net ::.
Jump to __KERNEL_CS:%eip to cause the GDT to be used. Now in [MDN Docs: Swift]
********** protected mode **********.
Reload all of the segment registers: Set the %ds, %es, %fs, and %gs registers to __KERNEL_DS.
#ifdef CONFIG_SMP
Reload the stack pointer segment only (%ss) with __KERNEL_DS.
#else /* not CONFIG_SMP */
Reload the stack pointer (%ss:%esp) with stack_start.
#endif /* CONFIG_SMP */
Clear the LDT pointer to 0.
Clear the processor's Direction Flag (DF) to 0 for gcc.
For CONFIG_SMP builds, if this is not the first (Bootstrap) CPU, call initialize_secondary(), which does not return. The secondary (AP) processor(s) are initialized and then enter idle state until processes are scheduled on them.
If this is the first or only CPU, call start_kernel(). (see below)
/* the calls above should never return, but in case they do: */
L6: jmp L6